Data processing systems normally require a plurality of internally generated processor clock signals derived from a reference clock signal, which processor clock signals have the same fixed periods and are available for clocking the operations of various components throughout the system. In a particular embodiment, for example, a first group of such internal processor clock signals are in phase with each other, while one or more other internal processor clock signals are either 90.degree. or 180.degree. out of phase with the first group.
In addition, many operating components in the system must be supplied with controllable gated clocked signals in order to be operable at the proper times, e.g., gated "select" signals for operating multiplexor units, gated "enabling" signals for operating latch units, and the like. Such latter units normally require the generation of gated signals as obtained from appropriate logic components, such as register programmed array logic (PAL) units. The operation of such PAL units inserts a time delay in the generation and supplying of the gated clock signals, which time delay, combined with other time delays inherent in the operation of the unit to which a gated signal is supplied, require a particular number of operating time cycles for the overall operation of generating and supplying such gated clock signals. If the time delays which arise in the generation and supplying of the gated signal can be reduced, in many cases the number of operating time cycles required for the overall operation of the gated unit can be reduced so as to improve the speed of operation of the processing system as a whole.